The present invention relates to a semiconductor memory device and a manufacturing method thereof.
Heretofore, demand for dynamic random access memories (DRAM) that has attained improvement for integration at a rate of four times per three year, has been increased more and more along with an explosive increase in the sales sum of personal computers in recent years. Already, mass production for 16 Mbits has passed the peak and development has been progressed at present for the mass production of 64 Mbits using a size of 0.2 xcexcm or less as the micro-fabrication in the next generation.
The memory cell for DRAM from 16 Kb to those put into products at present is constituted with a transistor 50 as a switch and a capacitor 51 for accumulating storage charges. Such a memory cell is referred to as 1 transistor cell. In the memory cell, the signal voltage read to data line BL is determined depending on the ratio of the capacitance Cs to the capacitor voltage 51 and the parasitic capacitance Cd of the data line BL. Further, since the signal voltage of the memory cell is charged to the voltage for the data line by reading the information, it is destructive reading. Accordingly, the memory cell of this type requires a refreshing operation of rewriting the data. WL in the figure shows a word line.
One of the greatest-subjects in the memory cell is insurance of necessary and sufficient capacitance Cs of the capacitor with two view points of the signal voltage of the memory cell and the durability to the soft errors. In order to solve the subject, the memory cell is constituted as a three dimensional structure and the height for the capacitor has been increased more and more along with micro-miniaturization in order to ensure necessary and sufficient accumulation capacitance. FIG. 2 shows an example of such a memory cell. FIG. 2 shows a cross section for a portion of a memory array 60 and a peripheral circuit 61. As described above, the height of the memory cell is increased for ensuring the capacitance thereof. In the example shown in FIG. 2, the capacitor 63 is mounted on a semiconductor substrate 77 disposed with a switching transistor 50. The capacitor has a lower electrode 73, an insulating layer 74, and an upper electrode 75. Since the capacitor is mounted on the semiconductor substrate, the height inevitably increases in order to ensure a desired capacitance for the capacitor. An example of such a memory cell is seen, for example, in FIG. 1 of 1999, IEDM, pp 45-48.
However, increase for the height of the capacitor results in large height difference between the memory array 60 and the peripheral circuit 61. This remarkably reduces the margin for various designs to the process including lithography. This directly leads to the increase of the manufacturing cost. It is inevitable that the problem will become severer in DRAM after 256 Mbits. In view of the background described above, it has been highly expected for a memory cell not requiring capacitor instead of the existent 1 transistor cell. As described above, it is anticipated a considerable difficulty for the attainment of DRAM after 256 Mbits of memory capacitance with the existent 1 transistor cell in view of a physical reason because of the increasing height of the capacitor.
Further, while an example of using a device that utilizes a multistable current state to a memory cell has also been reported, it has not yet been put to practical use at present. Such an example is described, for example, in U.S. Pat. Nos. 5,745,407 and 5,535,156.
The invention of the present application intends to drastically turn such current background.
In order to solve such problems, the invention of the present application provides a semiconductor memory device using a bistable diode not requiring a capacitor as a constituent element of the memory cell instead of the existent 1 transistor cell, as well as a manufacturing method thereof.
According to the invention of the present application, the cell area in semiconductor memory device is extremely small to enable high integration degree. Further, according to the invention of the present application, it can provide a semiconductor memory device requiring no refreshing and suitable to embedding with logics, as well as a manufacturing method thereof. More specifically, the invention of the present application can provide a random access memory (RAM) with extremely small memory cell area and capable of attaining high integration degree.
At first, for easy understanding, a basic concept of the invention of the present application is to be explained with reference to the drawings.
A bistable diode that can be used in the invention of the present application is a negative resistance element having at least a high impedance state and a low impedance state.
A specific structure in a typical example of a bistable diode that can be used in the invention of the present application has a basic structure as shown in FIG. 3A. That is, the basic structure thereof comprises a multi-layered structure of a conductive layer (1)/insulating layer (2)/n-type semiconductor layer (3)/p-type semiconductor layer (4). Substantially the same discussion can be applied also to a structure in which the order of layering is replaced between the n-type semiconductor (3) and the p-type semiconductor (4) excepting that the polarity is inverted. Typical examples of the n-type semiconductor layer (3) and the p-type semiconductor (4) are n-type silicon layer and p-type silicon layer, respectively. Accordingly, the n-type semiconductor layer (3) and the p-type semiconductor layer (4) are to be explained with silicon layers respectively. Further, the insulating layer can be constituted with plural insulating layers. This example is to be described later.
Now, in the structure shown in FIG. 3(a), a positive bias is applied to the p-type silicon 3. At the initial stage, an n-type silicon band is bent at the boundary of the insulating layer (2)/n-type silicon layer (3). However, since holes are not accumulated at the boundary thereof in this case, a depletion layer 5 is formed on the surface of semiconductor crystals. FIG. 3(b) is a band-structural view showing the state. The state in FIG. 3(b) shows a so-called deep depression state. As a result, most of the application voltage is applied to the surface depletion layer formed in the boundary of the insulator (2)/n-type silicon (3). Accordingly, since the voltage applied on the insulating layer (2) is weak, movement of the carriers by way of the insulating layer, for example, tunneling effect is inhibited. As a result, the memory cell is in a high impedance state. Reference numeral for each of the layers in FIG. 3(b) corresponds to the structure shown in FIG. 3(a). In the drawing, a small tunnel current 6 is shown by an arrow. Further, the state of the applied voltage to the insulating layer (2), so-called a tunnel film is depicted by reference numeral 9. The movement of carriers by way of the insulating layer is to be explained by means of movement by a so-called tunneling effect.
Further, when the voltage applied to the p-type silicon is increased, hole current from a PN-junction 7 formed in the inside of the substrate increases to form an inversion layer 8 at the boundary of the insulator (2)/n-type silicon (3). Accordingly, most of the application voltage is applied to the insulating layer (2). As a result, tunneling of electrons from the conductor (1) is enabled and since electrons injected from the conductor (1) neutralize donors of the n-type silicon layer (3), the barrier for the hole injection is further lowered and the current is further increased. Thus, the low impedance state of the memory cell is attained.
FIG. 3C shows a band structural view in this state. The reference numerals for each of the layers in FIG. 3(c) correspond to the structure in FIG. 3(a). In the figure, a large tunnel current 6 is depicted by a fat arrow.
As a result, the device shows a bistable state. Accordingly, when a load resistance is connected in series with the device exemplified in FIG. 3, there are present two stable points as shown in FIG. 4. Accordingly, a memory device can be constituted with such a constitution. FIG. 4 is a graph schematically showing operation characteristics of the device exemplified in FIG. 3 when a load resistance is connected in series therewith. In FIG. 4, the abscissa expresses voltage and the ordinate expresses current. All the unit are arbitrary units. FIG. 4 shows the characteristics in the high impedance state and the low impedance state described above and further shows a load line in a case of connecting a resistor. Then, FIG. 4 shows the two stable points described above as xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d.
FIG. 5 is a constitutional example of a memory cell array using the bistable diode. As shown in FIG. 5, memory cells 100 can be arranged at the intersections of word lines WL1, WL2 and bit lines BL1 and BL2. The memory cell 100 is constituted as described above with a conductive layer, an insulating layer, an n-type silicon layer and a p-type silicon layer. Reference numeral 101 denotes a load resistance for the diode. The load resistance 101 is sometimes designed specifically by a so-called parasitic resistance in view of the constitution of the semiconductor device. Accordingly, it will be apparent that the load resistance 101 also includes the resistance thus disposed in the specification of the present application.
As will be described specifically in subsequent examples, according to the invention of the present application, a memory cell of a minimum area can be realized theoretically. That is, memory cells are usually arranged in a matrix in a semiconductor memory device. Then, since the structure of the memory cell used in the invention of the present application is constituted with the diode having the bistable characteristic and the load resistance described above, when the word lines and the bit lines are laid out perpendicular to each other in the semiconductor memory device, the memory cell can be mounted within a region where the word line and the bit line intersect to each other. Accordingly, the invention of the present application can provide a memory cell with the required minimum occupying area in principle. It will be apparent that the occupying area is smaller compared with that of the existent memory cells. Specifically, the size is about one-half of the existent 1 transistor memory cell. Further, the invention according to the present application can attain a semiconductor memory device having a memory element with less junction leak current and of excellent characteristics.
Principal modes of the invention according to the present application are set forth below.
(1) A first mode is a semiconductor memory device characterized by comprising a semiconductor substrate; a memory cell array, disposed on the semiconductor substrate, having plural memory cells, word lines and data lines for selecting the memory cells; and a peripheral circuit disposed on the semiconductor substrate; wherein the memory cell has a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and a potential can be applied to the insulating layer that enables the movement of carriers by way of the multi-layer.
Usually, the plural memory cells are arranged in a matrix manner.
(2) A second mode is a semiconductor memory device characterized by comprising a semiconductor substrate; a memory cell array, disposed on the semiconductor substrate, having plural memory cells, word lines and data lines for selecting the memory cells; and a peripheral circuit disposed on the semiconductor substrate on the periphery of the memory cell array; wherein the memory cell has a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and the multi-layer of the memory cell has bistable characteristics for the resistance value.
(3) A third mode is a semiconductor memory device characterized by comprising a semiconductor substrate; a memory cell array, disposed on the semiconductor substrate, having plural memory cells, word lines and data lines for selecting the memory cells; and a peripheral circuit, disposed on the semiconductor substrate, which is constituted with plural insulated gate field effect transistors (MISFET) on the periphery of the memory cell array; wherein the memory cell has a multi-layer of a conductive layer, an insulating layer that enables the tunneling effect and plural semiconductor layers containing impurities, and the semiconductor layers containing impurities are present in the semiconductor substrate.
In this case, it is extremely important that the plural semiconductor layers containing the impurities are present in the semiconductor substrate. The characteristics of the invention according to the present application can be attained extremely favorably. That is, the embodiment of the invention according to the present application can provide the structure of MISS (Metal Insulator Semiconductor Switch) with characteristics of higher performance. The plural semiconductor layers containing the impurities can be confined electrically within the semiconductor substrate.
(4) A fourth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (3), wherein the plural semiconductor layers containing impurities constituting the memory cell have at least two semiconductor layers of different p-type and n-type conduction. This mode is a more actual mode of plural semiconductor layers containing the impurities. This mode shows a most typical constitution of the invention according to the present application. As described above, the order of layering the p-type semiconductor layer and the n-type semiconductor layer may be optional. Further, the plural semiconductor layers containing the impurities can also be constituted with more semiconductor layers.
(5) A fifth mode is a semiconductor memory device as defined in the forgoing paragraph (4), wherein a position of junction formed of the two semiconductor layers of different p-type and n-type conduction of the memory cell is shallower than the depth of a device isolation region formed in the semiconductor substrate. Since the junction position of both between the P-type and N-type semiconductor regions is shallower than the depth of the device isolation region, both of the P-type and N-type semiconductor regions are defined by the insulation region of the device isolation region. Accordingly, this constitution can separate the memory cell in a self-aligned manner by utilizing the device isolation region.
(6) A sixth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (4) and (5) described above, wherein the position for the PN junction of the memory cell is shallower than the depth of 0.3 xcexcm from the surface of the semiconductor substrate.
This mode shows practical and useful PN junction position in the field of the semiconductor device. In particular, this structure can define the position of the PN junction by the formation of the isolation insulating layer.
(7) A seventh mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (4) to (6), wherein at least one of the plural semiconductor layers containing impurities for forming the memory cell has a impurity concentration that is higher in the inside of the semiconductor substrate than on the surface of the semiconductor substrate.
Since the concentration of the impurities at the PN junction is increased by the constitution, the width of the depression layer is more narrowed. Accordingly, punch through of the region including the depletion layer can be suppressed. On the other hand, the impurity concentration is set lower at the boundary constituted of the insulating layer and the semiconductor layer than that at the inside. Accordingly, the switching voltage of the device can be lowered. That is, low voltage operation of the devices is enabled.
The low voltage operation is a useful characteristic for constituting the memory array using NDR (Negative Differential Resistance) using this semiconductor device.
(8) An eighth mode is a semiconductor memory device as defined in any one of the forgoing paragraphs (4) to (7), wherein an impurity concentration of the layer present in contact with the surface of the semiconductor substrate among the plural semiconductor layers containing impurities for forming the memory cell is 1xc3x971017 cmxe2x88x923 or less on the surface of the semiconductor substrate.
This mode shows the practical and useful range of the impurities concentration in the field of the semiconductor device.
(9) A ninth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (4) to (8), wherein a maximum impurity concentration of a layer present in adjacent with the surface of the semiconductor substrate among the plural semiconductor layers containing impurities for forming the memory cell is 1xc3x971017 cmxe2x88x923 or more.
This mode shows the practical and useful range of the impurities concentration in the field of the semiconductor device.
(10) A tenth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (4) to (9), wherein a maximum impurity concentration of the layer present in the inside of the semiconductor substrate among the plural semiconductor layers containing impurities for forming the memory cell is 1xc3x971017 cmxe2x88x923 or more.
(11) An eleventh mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (4) to (10), wherein a position of the PN junction of the memory cell is at a place deeper than a position at which an impurity concentration is maximum of a layer present in contact with the surface of the semiconductor substrate among the plural semiconductor layers containing impurities for forming the memory cell.
(12) A twelfth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (3), wherein the plural semiconductor layers containing impurities for forming the memory cell comprise two P-type layers putting an N-type layer therebetween, or two N-type layers putting a P-type layer therebetween.
(13) A thirteenth mode is a semiconductor memory device wherein two P-type layers and an N-type layer present apart from the surface of the semiconductor substrate among the three semiconductor layers containing impurities for forming the memory cell satisfy the conditions as defined in any one of the foregoing paragraphs (5) to (11).
Modes set forth below are extremely practical and useful embodiments when the memory cell according to the invention of the present application is incorporated as a semiconductor memory device. The concrete examples are to be explained in the columns of preferred embodiments.
(14) A fourteenth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (3) to (13), wherein the conductive layer of the memory cell is a conductive layer connected to a gate electrode of an insulate gate field effect transistor (MISFET) in the peripheral circuit.
(15) A fifteenth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (3) to (14), wherein the conductive layer of the memory cell comprises a multi-layer containing N-type or P-type polycrystal silicon.
(16) A sixteenth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (3) to (15), wherein the insulating layer of the memory cell is an insulating layer connected with an insulating layer of an insulated gate field effect transistor (MISFET) in the peripheral circuit.
(17) A seventeenth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (16), wherein the insulating layer of the memory cell is a multi-layer of insulating layers having different band gaps.
(18) An eighteenth mode is a semiconductor memory device as defined in the foregoing paragraph (17), wherein the insulating layer of the memory cell comprises a multi-layer of a silicon oxide layer and a silicon nitride layer and the silicon oxide layer is present in contact with a P-type semiconductor layer formed in the silicon substrate.
The following examples are useful examples upon manufacture of a semiconductor device having a memory array specifically.
(19) A nineteenth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (18), wherein at least one of plural semiconductor layers containing the impurities of the memory cell is present extending in a direction perpendicular to the word line in the semiconductor substrate.
(20) A twentieth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (19), wherein a layer in contact with the insulating layer for forming the memory cell among the plural semiconductor layers containing the impurities of the memory cell is present being separated for every memory cell.
(21) A twenty first mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (20), wherein a conductive plug is electrically connected to a layer formed to the lowest portion among the plural semiconductor layers containing impurities for forming the memory cell.
In this example, the planer region for each of the devices can be kept small by the use of the conductive plug.
(22) A twenty second mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (21), wherein a layer formed at the lowest portion among plural semiconductor layers containing impurities for forming the memory cell is electrically connected with a conductive layer extending in a direction perpendicular to the word lines in a planer arrangement.
(23) A twenty third mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (22), wherein the layer present extending in a direction perpendicular to the word line in the planer arrangement among the plural semiconductor layers containing the impurities of the memory cell is electrically connected with one of diffusion layers of the insulated gate field effect transistor (MISFET) formed in the semiconductor substrate and connected electrically with the conductive layer extending in the direction perpendicular to the word line in the planer arrangement to the other of the diffusion layers of the MISFET.
(24) A twenty fourth mode is a semiconductor memory device characterized by including plural memory arrays each comprising plural word lines; plural data lines arranged so as to intersect the plural word lines in a planer arrangement; plural memory cells which are disposed each at a desired intersection between the plural word lines and the plural data lines and each connected to the corresponding word line and corresponding data line; a common data line disposed in common with the plural data lines; and plural signal transmission means having a switching function for connecting the common data line to the plural data lines respectively; wherein the memory cell has a multi-layer of a conductive layer, an insulating layer and a plural semiconductor layers containing impurities and a potential can be applied to the insulating layer that enables movement of the carriers by way of the multi-layer.
(25) A twenty fifth mode is semiconductor memory device characterized by including plural memory arrays each comprising plural word lines; plural data lines arranged so as to intersect the plural word lines in a planer arrangement; plural memory cells which are disposed each at a desired intersection between the plural word lines and the plural data lines and each connected to the corresponding word line and corresponding data line, a common data line disposed in common with the plural data lines; and plural signal transmission means having a switching function for connecting the common data line to the plural data lines respectively; wherein the memory cell has a multi-layer of a conductive layer, an insulating layer and a plural semiconductor layers containing impurities and the multi-layer of the memory cell has a bistable characteristic of a resistance value.
(26) A twenty sixth modes a semiconductor memory device characterized by including plural memory arrays each comprising plural word lines; plural data lines arranged so as to intersect the plural word lines in a planer arrangement; plural memory cells which are disposed each at a desired intersection between the plural word lines and the plural data lines and each connected to the corresponding word line and corresponding data line; a common data line disposed in common with the plural data lines; and plural signal transmission means having a switching function for connecting the common data line to the plural data lines respectively; wherein the memory cell has a multi-layer of a conductive layer, an insulating layer enabling a tunnel effect and a plural semiconductor layers containing impurities, and the plural semiconductor layers containing the impurities are present in the semiconductor substrate.
(27) A twenty seventh mode is a semiconductor device as defined in any one of the foregoing paragraphs (1) to (26), wherein at least a memory cell and, further, the memory device are formed on a silicon on insulator substrate.
(28) A twenty eighth mode is a semiconductor memory device as defined in any one of the foregoing paragraphs (1) to (27), wherein plural bit lines have one sense amplifier in common in the memory cell array region.
(29) A twenty ninth mode is a semiconductor device having a bistable diode in a semiconductor substrate.
In this mode, the bistable diode is constituted not being stacked on the semiconductor substrate but being contained in the semiconductor substrate. Among all, it is important that the semiconductor layer region of the bistable diode is formed in the semiconductor substrate. That is, a desired portion of the prepared semiconductor substrate is used at least as a portion of the semiconductor layer of the bistable diode. It is of course possible to use a desired portion of the prepared semiconductor substrate as all of various semiconductor layers of the bistable diode. This example is novel and can utilize the bistable diode with a sufficiently effective characteristic.
In the specification of the present application, it is apparent that the semiconductor substrate also includes the substrate prepared by disposing an epitaxial layer on a desired semiconductor substrate.
(30) A thirtieth mode is a semiconductor memory device wherein the semiconductor device or the semiconductor memory device according to the invention of the present application is such that the memory device is disposed in the semiconductor substrate and the memory capacity is 256 Mbits or more.
In this mode, the memory device is constituted not being stacked on the semiconductor substrate but being contained in the semiconductor substrate. This mode is novel and the memory device can be utilized with a sufficiently effective characteristic. Then, according to the constitution of the invention of the present application, a semiconductor memory device having a memory capacity of 256 Mbits or more can be constituted while effectively insuring the memory characteristic, the switching characteristic or the regulation for the device occupying area.
In the same manner as explained for the foregoing paragraph (29), the memory device is constituted not being stacked on the semiconductor substrate, but being contained in the semiconductor substrate. Among all, it is important that the semiconductor layer region of the memory device is formed in the semiconductor substrate. That is, a desired portion of the prepared semiconductor substrate is used at least as a portion of the semiconductor layer of the memory device. It is apparent that a desired portion of the prepared semiconductor substrate can be used as all of various semiconductor layers of the memory device.
The invention of the present application can at first provide a semiconductor memory device in which the memory device is disposed in the semiconductor substrate and the storage capacity is 256 Mbits or more.
(31) A thirty first mode is a method of manufacturing a semiconductor memory device comprising a step of forming device isolation regions for electrically isolating devices to a semiconductor substrate; a step of forming an impurity diffusion layer in the substrate by implantation of ions at high energy in a memory cell array region and then forming an insulating layer on the surface of the substrate; a step of forming a word electrode in the memory cell array region and a gate electrode of an insulated gate field effect transistor (MISFET) in a peripheral circuit region; a step of etching a silicon substrate using a region covering the word electrode as at least an area corresponding to a mask, and thereby isolating the memory array for every cell; a step of depositing an insulating interlayer, then opening a contact hole and burying a conductive body into the contact; and a step of forming a bit line in the memory cell array region and a local interconnect layer in the peripheral circuit region.
The concrete method thereof is to be explained in the column for preferred embodiments.